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August 1996
NDT014L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology.This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation
modes.Thesedevices are particularly suited for low voltage
Features
2.8 A, 60 V. R DS(ON) = 0.2 ? @ V GS = 4.5 V
R DS(ON) = 0.16 ? @ V GS = 10 V.
High density cell design for extremely low R DS(ON) .
High power and current handling capability in a widely used
surface mount package.
applications such as DC motor control and DC/DC
conversion where fast switching, low in-line power loss, and
resistance to transients are needed.
_________________________________________________________________________________
D
D
G
D
S
G
S
Absolute Maximum Ratings
T A = 25°C unless otherwise noted
Symbol
V DSS
V GSS
Parameter
Drain-Source Voltage
Gate-Source Voltage
NDT014L
60
± 20
Units
V
V
I D
Drain Current
- Continuous
(Note 1a)
± 2.8
A
- Pulsed
± 10
P D
Maximum Power Dissipation
(Note 1a)
3
W
(Note 1b)
(Note 1c)
1.3
1.1
T J ,T STG
Operating and Storage Temperature Range
-65 to 150
°C
THERMAL CHARACTERISTICS
R θ JA
R θ JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
42
12
°C/W
°C/W
? 1997 Fairchild Semiconductor Corporation
NDT014L Rev.D
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